# FPGA, CPLD, 74xx loģikas >  BCD counter 7Seg_LED driver KODS

## Epis

Tā šeit ir mans Pilnais BCD counter (asinhronais reset, ir arī sinhronā reset koda gabals kurš vienkārši nav ieintegrēts) + 7segment LED driveris. ar papildus integrētu TEST kodu (23bit  ar kura palīdzību var vienkārši pārbaudīt vai tā loģika vispār strādā.

Kādēļ es tādu kodu taisīju, vienkārši tādēļ ka ZZZ neticēja ka var uztaisīt frekvences skaitītāju iekš 2$ lētas 64 cell CPLD, lūk šias tad ir pierā'dijums tam ka tas ir iespējams (vienīgi vaig stabilu 1-10Hz clock ārējo signālu) 
kods aizņem 59cells iekš CPLD šitas test kods aizņem 96 LE uz ciklon II fpga, jo tur ir integrēts papildus Test taimeris.
Top level fails: 


```
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity CPLD_led_driver is
 PORT (
CLOCK_24 : in std_logic;
CLK100 : OUT std_logic;
SW : IN std_logic_vector (2 downto 0);
HEX0 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0); 
HEX1 :OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
 
--switch: IN std_logic_vector (2 downto 0);
--Clock100ms : IN std_logic;
--SEG1_OUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); 
--Seg2_out: OUT STD_LOGIC_VECTOR(6 DOWNTO 0); 
BCDcounter : out std_logic_vector( 3downto 0);
BCDcounter2 : out std_logic_vector( 3downto 0);
BCDcary,Edge_T : out std_Logic);


end CPLD_led_driver;

Architecture BCD of CPLD_led_driver is

Component BCD_counter 
	PORT (
		D,En : in STD_logic;
		Q : OUT std_logic_vector(3 downto 0);
		C : out std_logic);
	end component;
Component impulse_generator is
	Port(
	clk,D : In STD_logic;
	q : OUT STD_LOGIC);
	end component;
	
	 signal Timer,Prescaler:  STD_logic_vector (22 downto 0); -- skaitāmā frekvence.
	-- 7ciparu bcd counteri.
	signal BCD1_timer: STD_logic_vector (3downto 0);
	signal BCD1_cary: std_logic;
	signal BCD2_timer: STD_logic_vector (3downto 0);
	signal BCD2_cary: std_logic;
	signal BCD3_timer: STD_logic_vector (3downto 0);
	signal BCD3_cary: std_logic;
	signal BCD4_timer: STD_logic_vector (3downto 0);
	signal BCD4_cary: std_logic;
	signal BCD5_timer: STD_logic_vector (3downto 0);
	signal BCD5_cary: std_logic;
	signal BCD6_timer: STD_logic_vector (3downto 0);
	signal BCD6_cary: std_logic;
	signal BCD7_timer: STD_logic_vector (3downto 0);
	signal BCD7_cary: std_logic;
	
	 signal BCD1: STD_LOGIC_VECTOR(3 DOWNTO 0);
	 signal BCD2: STD_LOGIC_VECTOR(3 DOWNTO 0);
	signal SEG1_OUT: STD_LOGIC_VECTOR(6 DOWNTO 0);
	signal SEG2_OUT: STD_LOGIC_VECTOR(6 DOWNTO 0);
	signal switch: std_logic_vector (2 downto 0);
	signal Edge,edge_V, En,D,clock100ms : std_logic;
	
begin
D<= CLOCK_24; -- 24Mhz clock signāls
Switch <=SW;
--HEX0<="1100000";
--HEX1<="1100000";
HEX0<= not SEG1_OUT;
HEX1<= not SEG2_OUT;
-- SSis koda gabals ir TEST 23bit counteris var griezt ārā.
process(D)
begin
if rising_edge(D) then
	prescaler<=prescaler +1;
		if prescaler = X"0" then
			if clock100ms ='1' then
		clock100ms <='0';
		else clock100ms <='1';
		end if;
	end if;
	end if;
end process;
clk100<=clock100ms;

--- BCD countera kods
BCD1_counter : BCD_counter   --- Pirmais BCD counteris
Port MAP( D=>D,En=>En, Q=>BCD1_timer ,C=>BCD1_cary);

BCDcounter <= BCD1_Timer;
BCDcounter2 <= BCD2_Timer;
BCDcary<= BCD1_cary;
BCD2_counter : BCD_counter  --- Otrais BCD counteris
Port MAP( D=>BCD1_cary,En=>En, Q=>BCD2_timer ,C=>BCD2_cary);

BCD3_counter : BCD_counter  --- 3 BCD counteris
Port MAP( D=>BCD2_cary,En=>En, Q=>BCD3_timer ,C=>BCD3_cary);

BCD4_counter : BCD_counter  --- 4 BCD counteris
Port MAP( D=>BCD3_cary,En=>En, Q=>BCD4_timer ,C=>BCD4_cary);

BCD5_counter : BCD_counter  --- 5 BCD counteris
Port MAP( D=>BCD4_cary,En=>En, Q=>BCD5_timer ,C=>BCD5_cary);

BCD6_counter : BCD_counter  --- 6 BCD counteris
Port MAP( D=>BCD5_cary,En=>En, Q=>BCD6_timer ,C=>BCD6_cary);

BCD7_counter : BCD_counter  --- 7 BCD counteris
Port MAP( D=>BCD6_cary,En=>En, Q=>BCD7_timer ,C=>BCD7_cary);

process(D)
begin
	if rising_edge(D) then
	Case Switch is
		when "001" => BCD1<=BCD1_timer;
					 BCD2<= BCD2_timer;
		when "010"=>BCD1 <=BCD3_timer;
					BCD2 <= BCD4_timer;
		when "100"=>BCD1 <=BCD5_timer;
					  BCD2<=BCD6_timer;
		when others =>  BCD1<=BCD7_timer;
					 BCD2<= "0000";
	end case;
end if;
end process;


process(edge)
begin
	if rising_edge(edge) then
		case BCD1 is
			when X"0" => SEG1_OUT<= "0111111";
			when X"1" => SEG1_OUT<= "0000110";
			when X"2" => SEG1_OUT<= "1011011";
			when X"3" => SEG1_OUT<= "1001111";
			when X"4" => SEG1_OUT<= "1100110";
			when X"5" => SEG1_OUT<= "1101101";
			when X"6" => SEG1_OUT<= "1111101";
			when X"7" => SEG1_OUT<= "0000111";
			when X"8" => SEG1_OUT<= "1111111";
			when X"9" => SEG1_OUT<= "1100111";
			when others => SEG1_OUT<= "0000000";
		end case;
	end if;
end process;

process(edge)
begin
	if rising_edge(edge) then
		case BCD2 is
			when X"0" => SEG2_OUT<= "0111111";
			when X"1" => SEG2_OUT<= "0000110";
			when X"2" => SEG2_OUT<= "1011011";
			when X"3" => SEG2_OUT<= "1001111";
			when X"4" => SEG2_OUT<= "1100110";
			when X"5" => SEG2_OUT<= "1101101";
			when X"6" => SEG2_OUT<= "1111101";
			when X"7" => SEG2_OUT<= "0000111";
			when X"8" => SEG2_OUT<= "1111111";
			when X"9" => SEG2_OUT<= "1100111";
			when others => SEG2_OUT<= "0000000";
		end case;
	end if;
end process;
--XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

process(D) -- Kods kas no Clock100ms uztaisa 1nu D tiksskki.
begin
	if rising_edge(D) then
		if clock100ms ='1' then 
			if edge_V ='0' then
				Edge <='1'; edge_V <='1';
				else Edge <='0'; 
			end if;
			else edge_V<= '0';
		end if;
	end if;
end process;
En<= Edge;
Edge_T<=Edge;

End BCD;
```

 papild fails kur ir BCD 1 cipara counteris ar carry izeju,+ asinhrono reset. + Impulse-generators(es viņu tā saucu) kas reaģē uz lēno 10Hz clock signāla Rising_edge un uzģenerē mazu impulsu priekš ātrākas darbības loģikas kādi 100-2000000 Hz lai ātrākā loģika varētu redzēt lānākās loģikas izmaiņas ātrāk, ir domāts priekš Sinhronā BCD countera reseta, kas nav ieintegrēts.


```
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity BCD_counter is
Port (
D,En : in STD_logic;
Q : OUT std_logic_vector(3 downto 0);
C : out std_logic);
end BCD_counter;

architecture BCD_C of BCD_counter is
signal BCD_timer : std_logic_vector (3 downto 0);
 signal BCD_cary : std_logic;

begin

process(D,En)
begin
if En ='1' then
	BCD_timer <="0000";
	else if rising_edge(D) then
		if BCD_timer ="1001" then 
			BCD_cary <= '1';
			BCD_timer <="0000";
			else BCD_timer <= BCD_timer +1; BCD_Cary <='0';
		end if;
		end if;
	end if;
end process;
Q<= BCD_timer;
C<= BCD_cary;

end BCD_C;

-- Papildus Kods kuru var izmantot lai Uztaisītu Sinhrou BCD countera RESET !!!

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Entity impulse_generator is
	Port(
	clk,D : In STD_logic;
	q : OUT STD_LOGIC);
	end impulse_generator;
architecture I_gen of impulse_generator is
signal Edge,edge_V : std_logic;
begin
process(D) -- Kods kas no Clock100ms uztaisa 1nu D tiksskki.
begin
	if rising_edge(D) then
		if clk ='1' then 
			if edge_V ='0' then
				Edge <='1'; edge_V <='1';
				else Edge <='0'; 
			end if;
			else edge_V<= '0';
		end if;
	end if;
end process;
q<= edge;
end I_gen;
```

----------

